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LTC1456 12-Bit Rail-to-Rail Micropower DAC with Clear Input
FEATURES
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DESCRIPTION
The LTC(R)1456 is a complete single supply, rail-to-rail voltage output, 12-bit digital-to-analog converter (DAC) in an SO-8 package. It includes a rail-to-rail output buffer amplifier and an easy-to-use 3-wire cascadable serial interface. The LTC1456 includes a CLR pin that asynchronously clears the DAC to zero scale. The LTC1456 has an internal 2.048V reference and a fullscale output of 4.095V. It operates on a 4.5V to 5.5V supply, dissipating 2.2mW. The low power supply current and the space saving SO-8 package make the LTC1456 ideal for battery-powered applications.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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SO-8 Package 12-Bit Resolution Buffered True Rail-to-Rail Voltage Output Asynchronous Clear Input Built-In Reference Schmitt Trigger On Clock Input Allows Direct Optocoupler Interface Power-On Reset Clears DAC to 0V 3-Wire Cascadable Serial Interface Maximum DNL Error: 0.5LSB Low Cost
APPLICATIONS
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Digital Calibration Industrial Process Control Automatic Test Equipment Cellular Telephones
TYPICAL APPLICATION
Functional Block Diagram: 12-Bit Rail-to-Rail DAC with Clear Input
8 2 DIN 1 CLK P 3 CS/LD 12-BIT SHIFT REG AND DAC LATCH VCC 4.5V TO 5.5V 2.048V
0.5
+
12-BIT DAC
-
DNL ERROR (LSB)
VOUT
7
RAIL-TO-RAIL VOLTAGE OUTPUT
4 DOUT TO OTHER DACS 6 CLR POWER-ON RESET GND 5
1456 TA01
U
U
U
Differential Nonlinearity vs Input Code
0
-0.5 0 512 1024 1536 2048 2560 3072 3584 4095 CODE
1456 TA02
1
LTC1456 ABSOLUTE MAXIMUM RATINGS
VCC to GND .............................................. - 0.5V to 7.5V Logic Inputs to GND ................................ - 0.5V to 7.5V VOUT .............................................. - 0.5V to VCC + 0.5V Maximum Junction Temperature ......... - 65C to 125C Operating Temperature Range LTC1456C ............................................ 0C to 70C LTC1456I ........................................ - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
PACKAGE/ORDER I FOR ATIO
TOP VIEW CLK 1 DIN 2 CS/LD 3 DOUT 4 N8 PACKAGE 8-LEAD PDIP 8 7 6 5 VCC VOUT CLR GND
ORDER PART NUMBER LTC1456CN8 LTC1456IN8 LTC1456CS8 LTC1456IS8 S8 PART MARKING 1456 1456I
S8 PACKAGE 8-LEAD PLASTIC SO
TJMAX = 125C, JA = 100C/W (N8) TJMAX = 125C, JA = 150C/W (S8)
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
VCC = 4.5V to 5.5V, VOUT unloaded, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL DAC Resolution DNL INL VOS VOSTC VFS VFSTC Differential Nonlinearity Integral Nonlinearity Offset Error Offset Error Temperature Coefficient Full-Scale Voltage Full-Scale Voltage Temperature Coefficient Positive Supply Voltage Supply Current Short-Circuit Current Low Short-Circuit Current High Output Impedance to GND AC Performance Voltage Output Slew Rate Voltage Output Settling Time Digital Feedthrough (Note 2) (Notes 2, 3) to 0.5LSB
q q
PARAMETER
CONDITIONS
MIN 12
TYP
MAX
UNITS Bits
Guaranteed Monotonic (Note 1) TA = 25C (Note 1) TA = 25C
q q q
0.5 3.5 4 12 18 15
V/C 4.125 4.145 V V ppm/C
TA = 25C
q
4.065 4.045
4.095 4.095 24
Power Supply VCC ICC For Specified Performance (Note 4) VOUT Shorted to GND VOUT Shorted to VCC Input Code = 0
q q
4.5 430
5.5 650 120 120 40 120
Op Amp DC Performance
q q q
0.4
1.0 14 0.3
nV * s
2
U
LSB LSB LSB mV mV V A mA mA V/s s
W
U
U
WW
W
LTC1456
ELECTRICAL CHARACTERISTICS
VCC = 4.5V to 5.5V, VOUT unloaded, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL Digital I/O VIH VIL VOH VOL ILEAK CIN Switching t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 DIN Valid to CLK Setup DIN Valid to CLK Hold CLK High Time CLK Low Time CS/LD Pulse Width LSB CLK to CS/LD CS/LD Low to CLK DOUT Output Delay CLK Low to CS/LD Low CLR Pulse Width CLOAD = 15pF, VCC = 5V
q q q q q q q q q q
PARAMETER Digital Input High Voltage Digital Input Low Voltage Digital Output High Voltage Digital Output Low Voltage Digital Input Leakage Digital Input Capacitance
CONDITIONS
q q
MIN 2.4
TYP
MAX
UNITS V
0.8 VCC - 1.0 0.4 10 10 40 0 40 40 50 40 20 150 20 65
V V V A pF ns ns ns ns ns ns ns ns ns ns
IOUT = - 1mA, DOUT Only IOUT = 1mA, DOUT Only VCC = 5V, VIN = GND to VCC Guaranteed by Design. Not Subject to Test.
q q q q
The q denotes specifications which apply over the full operating temperature range. Note 1: Nonlinearity is defined from the first code that is greater than or equal to the maximum offset specification to code 4095 (full scale). Note 2: Load is 5k in parallel with 100pF.
Note 3: DAC switched between all 1s and the code corresponding to VOS for the part. Note 4: Digital inputs at 0V or VCC.
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LTC1456 TYPICAL PERFORMANCE CHARACTERISTICS
Differential Nonlinearity (DNL)
0.5 0.4 0.3
INL ERROR (LSB)
2.0 1.6 1.2 0.8 0.4 0 - 0.4 - 0.8 -1.2 -1.6 - 2.0
0.2
DNL (LSB)
0.1 0 - 0.1 - 0.2 - 0.3 - 0.4 - 0.5 0 512 1024 1536 2048 2560 3072 3584 4095 CODE
1456 G01
VCC - VOUT (V)
Minimum Output Voltage vs Output Sink Current
700
1.750
OUTPUT PULL-DOWN VOLTAGE (mV)
125C 600 500 25C 400 300 200 100 0 0 2 8 10 12 14 16 18 20 46 OUTPUT SINK CURRENT (mA)
1456 G04
SUPPLY CURRENT (mA)
OUTPUT SWING (V)
- 55C
Output Swing vs Load Resistance
4.5 CODE: ALL 1s 4.0 0.8 3.5
OUTPUT SWING (V)
SUPPLY CURRENT (A)
OFFSET VOLTAGE (mV)
3.0 2.5 2.0 1.5 1.0 0.5 0 10 100 1k LOAD RESISTANCE () 10k
1456 G07
4
UW
RL
Integral Nonlinearity (INL)
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0
0 512 1024 1536 2048 2560 3072 3584 4095 CODE
1456 G02
Minimum Supply Headroom for Full Output Swing vs Load Current
VOUT < 1LSB CODE: ALL 1s VOUT = 4.095V
0
5
20 15 10 LOAD CURRENT (mA)
25
30
1456 G03
Supply Current vs Logic Input Voltage
4.5
ALL DIGITAL INPUTS TIED TOGETHER 1.615 1.480 1.345 1.210 1.075 0.940 0.805 0.670 0.535 0.400 0 0.5 1 1.5 2 2.5 3 3.5 4 LOGIC INPUT VOLTAGE (V) 4.5 5
1456 G05
Output Swing vs Load Resistance
CODE: ALL 0s 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 10 100 1k LOAD RESISTANCE () 10k
1456 G06
VCC RL
Offset Voltage vs Temperature
0.9
Supply Current vs Temperature
550 540 530 520 510 500 490 480 470 460 VCC = 4.5V VCC = 5V VCC = 5.5V
0.7 0.6 0.5 0.4 0.3 - 55
- 25
5 35 65 TEMPERATURE (C)
95
125
1456 G08
450 - 55
- 25
35 65 5 TEMPERATURE (C)
95
125
1456 G09
LTC1456
PIN FUNCTIONS
CLK (Pin 1): The Serial Interface Clock. Internal Schmitt trigger on this input allows direct optocoupler interface. DIN (Pin 2): The Serial Interface Data. Data on the DIN pin is latched into the shift register on the rising edge of the serial clock. CS/LD (Pin 3): The Serial Interface Enable and Load Control. When CS/LD is low the CLK signal is enabled, so the data can be clocked in. When CS/LD is pulled high, data is loaded from the shift register into the DAC register, updating the DAC output. When CS/LD is high the CLK is disabled internally. DOUT (Pin 4): The Output of the Shift Register Which Becomes Valid on the Rising Edge of the Serial Clock. GND (Pin 5): Ground. CLR (Pin 6): The Clear Input. When pulled low, this pin asynchronously clears the internal shift and DAC registers to zero scale. Should be tied high for normal operation. VOUT (Pin 7): The Buffered DAC Output. VCC (Pin 8): The Positive Supply Input. 4.5V VCC 5.5V. Requires a bypass capacitor to ground.
BLOCK DIAGRA
CLK 1
DIN 2 12-BIT SHIFT REGISTER CS/LD 3
DOUT 4
TI I G DIAGRA
CLK t9 DIN
B0 PREVIOUS WORD
CS/LD
DOUT
W
W
U
U
UW
U
2.048V
8 VCC
LD DAC REGISTER 12-BIT DAC
+
7 VOUT
-
POWER-ON RESET
6 CLR 5 GND
1146 BD
t1
t2
t6
t7
t4
t3
B11 MSB
B10
B1
B0 LSB
t8
t5
B11 PREVIOUS WORD
B10
B1
B0
B11 CURRENT WORD
1456 TD
5
LTC1456
DEFI ITIO S
Resolution (n): Resolution is defined as the number of digital input bits, n. It defines the number of DAC output states (2n) that divide the full-scale range. The resolution does not imply linearity. Full-Scale Voltage (VFS): This is the output of the DAC when all bits are set to 1. Voltage Offset Error (VOS): The theoretical voltage at the output when the DAC is loaded with all zeros. The output amplifier can have a true negative offset, but because the part is operated from a single supply, the output cannot go below zero. If the offset is negative, the output will remain near 0V resulting in the transfer curve shown in Figure 1. The offset of the part is measured at the code that corresponds to the maximum offset specification: VOS = VOUT - [(Code * VFS)/(2n - 1)] Least Significant Bit (LSB): One LSB is the ideal voltage difference between two successive codes. LSB = (VFS - VOS)/(2n - 1) = (VFS - VOS)/4095 LSB = 4.095/4095 = 1mV Integral Nonlinearity (INL): End-point INL is the maximum deviation from a straight line passing through the end-points of the DAC transfer curve. Because the part operates from a single supply and the output cannot go below zero, the linearity is measured between full scale and the code corresponding to the maximum offset specification. The INL error at a given input code is calculated as follows: INL = [VOUT - VOS - (VFS - VOS)(code/4095)]/LSB VOUT = The output voltage of the DAC measured at the given input code Differential Nonlinearity (DNL): DNL is the difference between the measured change and the ideal 1LSB change between any two adjacent codes. The DNL error between any two codes is calculated as follows: DNL = (VOUT - LSB)/LSB VOUT = The measured voltage difference between two adjacent codes Digital Feedthrough: The glitch that appears at the analog output caused by AC coupling from the digital inputs when they change state. The area of the glitch is specified in (nV)(sec).
6
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OUTPUT VOLTAGE
NEGATIVE OFFSET
0V
DAC CODE
1456 F01
Figure 1. Effect of Negative Offset
LTC1456
OPERATIO
Serial Interface
The data on the DIN input is loaded into the shift register on the rising edge of the clock. The MSB is loaded first. The DAC register loads the data from the shift register when CS/LD is pulled high. The CLK is disabled internally when CS/LD is high. Note: CLK must be low before CS/LD is pulled low to avoid an extra internal clock pulse. When CLR is pulled low it asynchronously resets the shift and DAC registers to all zeros. The buffered output of the 12-bit shift register is available on the DOUT pin which swings from GND to VCC. Multiple LTC1456s may be daisy-chained together by connecting the DOUT pin to the DIN pin of the next chip, while the CLK
TYPICAL APPLICATION
The circuit below shows a digitally programmable current source from an external voltage source using an external op amp, an LT (R)1077 and an NPN transistor (2N3440). Any digital word from 0 to 4095 is loaded into the LTC1456 and its output correspondingly swings from 0V to 4.095V. In the configuration shown, this voltage will be forced across the resistor RA. If RA is chosen to be 410 the output current will range from 0mA at zero scale to 10mA at full scale. The minimum voltage for VS is determined by the load resistor RL and Q1's VCESAT voltage. With a load resistor of 50, the voltage source can be as low as 5V.
12-Bit 5V Single Supply Voltage Output DAC
4.5V TO 5.5V
CLR P CLK DIN CS/LD
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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and CS/LD signals remain common to all chips in the daisy chain. The serial data is clocked to all of the chips, then the CS/LD signal is pulled high to update all of them simultaneously. Voltage Output The LTC1456's rail-to-rail buffered output can source or sink 5mA over the entire operating temperature range while pulling to within 300mV of the positive supply voltage or ground. The output swings to within a few millivolts of either supply rail when unloaded and has an equivalent output resistance of 40 when driving a load to the rails. The output can drive 1000pF without going into oscillation.
0.1F DIN P CLK LTC1456 CS/LD DOUT CLR TO NEXT DAC FOR DAISY-CHAINING
1456 TA03
VCC VOUT OUTPUT 0V TO 4.095V
GND
Digitally Programmable Current Source
5V VS + 5V TO 100V FOR RL 50 D * 4.095 IOUT = IN 0mA TO 10mA 4096 * RA
0.1F VCC LTC1456 GND VOUT
RL
+
LT1077 Q1 2N3440
-
RA 410
1456 TA04
7
LTC1456
PACKAGE DESCRIPTION
0.300 - 0.325 (7.620 - 8.255)
0.009 - 0.015 (0.229 - 0.381)
0.065 (1.651) TYP 0.005 (0.127) MIN 0.125 (3.175) MIN 0.015 (0.380) MIN
0.018 0.003 0.100 0.010 (0.457 0.076) (2.540 0.254) *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
(
+0.025 0.325 -0.015 +0.635 8.255 -0.381
)
0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254)
0- 8 TYP 0.228 - 0.244 (5.791 - 6.197) 0.150 - 0.157** (3.810 - 3.988)
0.016 - 0.050 0.406 - 1.270
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
RELATED PARTS
PART NUMBER LTC1257 LTC1446/LTC1446L LTC1450/LTC1450L LTC1451 LTC1452 LTC1453 LTC1454/LTC1454L LTC1458/LTC1458L DESCRIPTION Single 12-Bit VOUT DAC, Full Scale: 2.048V, VCC: 4.75V to 15.75V, Reference Can Be Overdriven Up to 12V, i.e., FSMAX = 12V Dual 12-Bit VOUT DACs in SO-8 Package Single 12-Bit VOUT DACs with Parallel Interface Single Rail-to-Rail 12-Bit DAC, Full Scale: 4.095V, VCC: 4.5V to 5.5V, Internal 2.048V Reference Brought Out to Pin Single Rail-to-Rail 12-Bit VOUT Multiplying DAC, VCC: 2.7V to 5.5V Single Rail-to-Rail 12-Bit VOUT DAC, Full Scale: 2.5V, VCC: 2.7V to 5.5V Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality Quad 12 Bit Rail-to-Rail Output DACs with Added Functionality COMMENTS 5V to 15V Single Supply, Complete VOUT DAC in SO-8 Package LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1450: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1450L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Same as LTC1456 Except REF Out Pin Replaces CLR Pin Low Power, Multiplying VOUT DAC with Rail-to-Rail Buffer Amplifier in SO-8 Package 3V, Low Power, Complete VOUT DAC in SO-8 Package LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
1456fs, sn1456 LT/TP 0697 7K * PRINTED IN USA (c) LINEAR TECHNOLOGY CORPORATION 1996
8
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417 q (408) 432-1900 FAX: (408) 434-0507q TELEX: 499-3977 q www.linear-tech.com
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Dimensions in inches (millimeters) unless otherwise noted. N8 Package 8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.045 - 0.065 (1.143 - 1.651) 0.130 0.005 (3.302 0.127) 0.400* (10.160) MAX 8 7 6 5
0.255 0.015* (6.477 0.381)
1
2
3
4
N8 0695
S8 Package 8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 - 0.197* (4.801 - 5.004) 0.053 - 0.069 (1.346 - 1.752) 0.004 - 0.010 (0.101 - 0.254) 8 7 6 5
0.014 - 0.019 (0.355 - 0.483)
0.050 (1.270) BSC
SO8 0695
1
2
3
4

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